Memory Level Parallelism: An Overlooked Path to Processor Efficiency 19/09/16 KB L.T 1.5 11.15Published: Friday, 16 September 2016
Monday 19th September 2016 in Kilburn L.T. 1.5 at 11.15am
Memory Level Parallelism: An Overlooked Path to Processor Efficiency
Speaker: Trevor Carlson
Host: Mikel Lujan
Historically, processor performance has been pursued in the form of general-purpose instruction level parallelism (ILP) at a significant resource cost. As the benefits of Dennard Scaling come to an end, the limited gains from newer process technologies will no longer allow for these increasingly complex and power-hungry methods to improve performance. One potential solution, hardware acceleration, is an important trend in computer architecture, but recent work has shown that the use of accelerators will only exacerbate the problem by increasing the amount of irregular, difficult to predict code to be executed on the cores. Computer architects need a solution that addresses two critical concerns: (1) high-performance, energy efficient computation and (2) fast and flexible software as commonly seen in data centers and mobile devices.
In this seminar, I discuss innovative microarchitectures to improve performance in the presence of these processor power limits. I present my recent work which focuses on Memory Level Parallelism (MLP) and a novel learning algorithm to allow the hardware to optimize the use of these precious resources. In addition, I discuss a new processor type that, by leveraging compiler techniques to improve MLP along with hardware assistance, allows for improved performance and energy efficiency by extending the reach of hardware past traditional limits. Taken together, these approaches demonstrate how a focus on MLP improves efficiency and performance for both general-purpose (and cloud-computing) style processors as well as highly efficient, IoT-style processors.
Trevor E. Carlson is a postdoctoral researcher at Uppsala University. He received his B.S. and M.S. degrees from Carnegie Mellon University in 2002 and 2003, and his Ph.D. from Ghent University in 2014. While a staff engineer at IBM he helped to author 4 issued patents between 2003 and 2007, and later investigated efficient architectures for embedded 3D-stacked systems at IMEC. He has over 13 years of computer architecture experience covering both industry and academia, with publications at leading publications in computer architecture. His work on sampling and modeling has seen two Best Paper Awards and two nominations for Best Paper. He co-developed the Sniper Multi-core Simulator which is being used by hundreds of researchers to perform cycle-level simulation for performance and power evaluation of next generation systems. His research interests include highly-efficient microarchitectures, hardware/software co-design, performance modeling and fast and scalable simulation methodologies.